{"id":813,"date":"2024-07-12T18:20:37","date_gmt":"2024-07-12T09:20:37","guid":{"rendered":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/?page_id=813"},"modified":"2024-07-12T18:20:37","modified_gmt":"2024-07-12T09:20:37","slug":"dept5-3","status":"publish","type":"page","link":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/department\/dept5\/dept5-3\/","title":{"rendered":"Research"},"content":{"rendered":"
\n

Low Power Design of Analog High-Frequency Integrated Circuits<\/span><\/h3>\n

\n\t\tIn today’s society, semiconductor integrated circuits, which are essential for modern living, demand continuous
\n\t\tperformance improvement. However, for mobile applications and in pursuit of a low-carbon society, there is also
\n\t\ta need to balance conflicting characteristics such as miniaturization and reduced power consumption. This
\n\t\tresearch primarily focuses on communication systems, which are often performance bottlenecks, and aims to
\n\t\tdevelop circuit design techniques that reconcile these opposing characteristics. From the initial design phase
\n\t\tto prototyping and evaluation, our research contributes to enhancing the performance of semiconductor devices,
\n\t\tmeeting the high demand both domestically and internationally.\n\t<\/p>\n

\t
\n\t\tWeb site (ICPKG) Lab.<\/a>
\n\t<\/span><\/p>\n

\n
\n\t\t\t\"\"<\/p>\n

\n\t\t\t\tSemiconductor Integrated Circuit Design Examples:
\n\t\t\t\t[Top Left] High-Efficiency Driver for Optical Communication (180nm CMOS)
\n\t\t\t\t[Top Right] InP Optical Integrated Circuit for Terahertz Wireless Communication
\n\t\t\t\t[Bottom] Low-Power On-Chip Communication System (90nm CMOS)\n\t\t\t<\/p>\n<\/p><\/div>\n<\/p><\/div>\n

Noise Reduction in Image Sensors<\/span><\/h3>\n

\n\t\tIn Image Sensors used for video recording and machine recognition, noise can degrade image quality and cause
\n\t\terrors in automated recognition. To understand the mechanism behind noise generation and to mitigate it, we
\n\t\tcombine experimental evaluation and computer simulations to study the behavior of impurities and defects in the
\n\t\tsemiconductor, which are the root causes of noise. Additionally, we work to establish noise reduction techniques
\n\t\tthat contribute to the enhancement of image sensor performance.\n\t<\/p>\n

\t
\n\t\tWeb site (Semiconductor-Process Evaluation Lab.,Suzuki Research Group)<\/a>
\n\t\tIntroduction of cleanroom (Youtube)<\/a>
\n\t<\/span><\/p>\n

\n
\n\t\t\t\"\"<\/p>\n

\n\t\t\t\tSchematic Diagram of an Image Sensor (Left) and Examples of White Spot and Dark Current Images (Right)\n\t\t\t<\/p>\n<\/p><\/div>\n<\/p><\/div>\n

Energy Storage and Conversion Materials<\/span><\/h3>\n

\n\t\tDielectrics possess the ability to instantaneously store and release electrical energy, making them
\n\t\tindispensable for the high-speed and stable operation of semiconductor devices. Moreover, some dielectrics have
\n\t\tthe capacity to convert stress or light into electrical energy through energy conversion processes. These
\n\t\tfunctionalities are intricately linked to the electronic states, crystal structures, lattice defects, and domain
\n\t\tstructures of materials. Through a collaborative approach that combines experimental research and theoretical
\n\t\tcalculations, we focus on understanding the behavior of atoms and electrons to design novel dielectric
\n\t\tmaterials. We synthesize ceramics, thin films, and single crystals, contributing to the development of new
\n\t\tmaterials that will advance next-generation semiconductor devices and energy conversion devices.\n\t<\/p>\n

\t
\n\t\tWeb site (Energy Material\/Functional
\n\t\t\tMaterials Lab.)<\/a>
\n\t<\/span><\/p>\n

\n
\n\t\t\t\"\"<\/p>\n

\n\t\t\t\tHierarchical Structure of Barium Titanate Ferroelectric Ceramic, from Micrometer to Atomic Scales. Trace
\n\t\t\t\tamounts of impurity elements (Fe) and oxygen vacancies (VO) also have a significant impact on its
\n\t\t\t\tproperties.\n\t\t\t<\/p>\n<\/p><\/div>\n<\/p><\/div>\n

Examining the Source of Functionality at the Nano and Atomic Scales<\/span><\/h3>\n

\n\t\tIn our research group, we aim to uncover the mechanisms behind the functioning and malfunctioning of
\n\t\tsemiconductor devices. Our goal is to contribute to the development of new devices and the enhancement of their
\n\t\tperformance based on this understanding. To conduct our research, we utilize tools such as Scanning Transmission
\n\t\tElectron Microscopy (STEM), which allows us to observe materials at the atomic and electron scale, as well as
\n\t\tfirst-principles calculations, which enable simulations at the atomic and electron scale.\n\t<\/p>\n

\n\t\tFor example, in the illustration provided, we elucidated the atomic-level structure of grain boundaries in zinc
\n\t\toxide (ZnO), a known oxide semiconductor. These grain boundaries were found to be hindering the flow of current.
\n\t\tOur research aims to uncover such detailed structures and mechanisms that influence semiconductor behavior,
\n\t\tpaving the way for advancements in semiconductor technology.<\/p>\n

\n\t\t
\n\t\t\tWeb site (Functional Nanostructures
\n\t\t\t\tLaboratory)<\/a>
\n\t\t<\/span><\/p>\n

\n
\"\"<\/div>\n<\/p><\/div>\n

Next-Generation Compound Semiconductor Devices<\/span><\/h3>\n

\n\t\tThe development of next-generation semiconductor materials with superior properties compared to conventional
\n\t\tsemiconductor materials is progressing. However, these materials have only been practically applied in specific
\n\t\tdevice structures. This is primarily because the surface and interface properties of next-generation
\n\t\tsemiconductor materials are not well understood. The surface and interface properties of semiconductors are
\n\t\tclosely related to transistor operational stability. Therefore, evaluating the electronic properties of the
\n\t\tjunction interfaces, including the surface, and developing process technologies based on the insights gained,
\n\t\tdirectly contributes to a fundamental understanding of material properties and improvements in device
\n\t\tperformance.\n\t<\/p>\n

\n\t\tAs a result, we are engaged in the development of innovative evaluation methods for the surface and interface
\n\t\tproperties of next-generation semiconductor devices, which are challenging to assess using conventional
\n\t\ttechniques. Additionally, we are working on process technology development to realize next-generation
\n\t\tsemiconductor devices.<\/p>\n

\n\t\t
\n\t\t\tWeb site (Prof. Zenji Yatabe,
\n\t\t\t\tResearchmap)<\/a>
\n\t\t<\/span><\/p>\n

\n
\n\t\t\t\"\"<\/p>\n

\n\t\t\t\tEnergy band diagram of a next-generation compound semiconductor device (left) and measurement of
\n\t\t\t\telectronic properties (right)\n\t\t\t<\/p>\n<\/p><\/div>\n<\/p><\/div>\n

Three-Dimensional Integrated Circuit (3D-IC) System Design Technology<\/span><\/h3>\n

\n\t\tOur research focuses on the design technology for LSI chip integration systems using three-dimensional stacking
\n\t\twith Through-Silicon-Vias (TSV) to achieve higher integration, increased chip-to-chip communication capacity and
\n\t\tspeed, and reduced power consumption. Traditionally, semiconductor LSIs, along with other components, are placed
\n\t\tin a planar arrangement on printed circuit boards or interposers (silicon chips for wiring).\n\t<\/p>\n

\n\t\tIn our research, we target LSI chip integration systems based on three-dimensional stacking with TSVs. We aim to
\n\t\tdevelop design techniques that modularize and integrate various components within the target system, including
\n\t\tmicroprocessors, software, dedicated hardware (digital logic circuits), sensors, actuators, communication
\n\t\tmodules, and power sources. This approach allows us to simulate and emulate the performance and power
\n\t\tconsumption of the system during application operations before manufacturing, enabling thorough verification.<\/p>\n

\n\t\t
\n\t\t\tWeb site (ICPKG) Lab.<\/a>
\n\t\t<\/span><\/p>\n

\n
\n\t\t\t\"\"<\/p>\n

\n\t\t\t\tThree-Dimensional Stacked LSI System Design Technology: [Left] Concept of componentization of LSI chips
\n\t\t\t\tand system integration through chip-to-chip communication, [Right] Example of a Three-Dimensional
\n\t\t\t\tStacked LSI System Emulator using FPGA.\n\t\t\t<\/p>\n<\/p><\/div>\n<\/p><\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"Low Power Design of Analog High-Frequency Integrated Circuits In today’s society, semiconductor integrat… View Article<\/a>","protected":false},"author":1,"featured_media":0,"parent":805,"menu_order":3,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-813","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/pages\/813","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/comments?post=813"}],"version-history":[{"count":1,"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/pages\/813\/revisions"}],"predecessor-version":[{"id":814,"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/pages\/813\/revisions\/814"}],"up":[{"embeddable":true,"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/pages\/805"}],"wp:attachment":[{"href":"https:\/\/www.eng.kumamoto-u.ac.jp\/english\/wp-json\/wp\/v2\/media?parent=813"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}